The present invention relates to a priority controller for determining priorities of request signals from a plurality of request circuits so as to select the request circuit having the highest priority.
In general, in acquisition control and interrupt control of a main memory or a system bus in a data processing system, a circuit (i.e., controlling means) is required to determine the priority levels of request signals from a plurality of request circuits (i.e., request devices) and then to find the priorities of the request circuits. Two priority determining systems are generally known. One of them comprises gate circuits which predetermine the relative priority levels of request signals from request circuits. The other system is of a daisy-chaining type and includes request circuits, in which an acknowledge signal is transferred from a common module to the original request circuit through any other request circuits which precede the original request circuit. More specifically, each of the request circuits preceding the original request circuit receives the acknowledge signal from the immediately preceding one and sends it to the immediately following request circuit. In the daisy-chaining system, any request circuit that receives the acknowledge signal has a higher priority than the immediately following request circuit.
However, these two types of priority determining systems cannot modify the priority levels, resulting in poor flexibility in acquisition control and interrupt control of the main memory and the system bus. A low-priority request circuit (request device) must often wait for a long period until its request is permitted. As a result, a plurality of request circuits having a time limit cannot be used. In particular, in the second priority determining system, it takes a long time to transmit the acknowledge signal to the original request circuit.